1. Field of the Invention
The present invention relates to a semiconductor device comprising a through-hole electrode and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Conventionally, the mainstream of semiconductor device configuration has been that a single semiconductor device is equipped with a single semiconductor silicon layer. In recent years, however, there have been proposed such semiconductor device configuration in which a single semiconductor device is equipped with a plurality of semiconductor silicon layers. More specifically, it is possible to enhance the capabilities of a semiconductor device, including the processing speed, while reducing the size and weight of the semiconductor device as a whole by mounting a plurality of semiconductor silicon layers in a multilayered manner within a single semiconductor device.
When manufacturing this semiconductor device equipped with a plurality of semiconductor silicon layers, it is necessary to laminate and electrically connect the semiconductor silicon layers to one another within the semiconductor device. Hence, as a semiconductor device in which a plurality of semiconductor silicon layers are electrically connected to one another, Japanese Patent Laid-Open No. 2005-93486 proposes a semiconductor device, in which through-hole electrodes are formed inside via holes penetrating through the semiconductor silicon layers within the semiconductor device and these through-hole electrodes are coupled with one another, and a method for manufacturing the semiconductor device.
Japanese Patent Laid-Open No. 2005-93486 (FIGS. 33 to 38) shows a method for manufacturing through-hole electrodes according to this related art. First, as shown in FIG. 33A, interlayer insulating film 153 (made of, for example, a silicon dioxide film or a silicon nitride film), pad electrode 155 (made of, for example, aluminum), passivation film 157 (made of, for example, a silicon dioxide film, a silicon nitride film, or a silicon oxynitride film) are successively formed on a surface of silicon substrate 151. Next, an opening is formed on passivation film 157 to have a surface of pad electrode 155 exposed from this opening.
Next, after conducting a probe test, the rear surface of silicon substrate 151 is polished so that the silicon substrate is thinned down to a thickness of at least 300 μm and so on. Next, surface protection film 161 (for example, a silicon dioxide film) is formed on silicon substrate 151, so as to cover pad electrode 155 and passivation film 157.
Next, as shown in FIG. 33B, silicon dioxide film 163 is formed on the entire rear surface of polished silicon substrate 151. Next, there is formed first resist mask 165 including opening 167 at a position corresponding to pad electrode 155 on the rear surface of silicon substrate 151 (FIG. 33C). Using this resist mask 165 as a mask, silicon dioxide film 163 is etched to form hard mask 163′ including opening 167 at a position corresponding to pad electrode 155, as shown in FIG. 34A.
Next, as shown in FIG. 34B, resist mask 165 is removed. After this, silicon substrate 151 is etched using this hard mask 163′ as a mask to form opening 169 including interlayer insulating film 153 shown in FIG. 34C as the bottom face thereof. The etching of this silicon substrate 151 is carried out by dry etching using an etching gas such as an SF6 or SF6/O2-based etching gas.
Subsequently, after removing hard mask 163′ as shown in FIG. 35A, insulating film 171 (for example, a silicon dioxide film) is formed to a thickness of approximately 1 μm on the entire rear surface of silicon substrate 151 in which this opening 169 has been formed, as shown in FIG. 35B. After this, the bottom face of opening 169 is exposed as shown in FIG. 35C, and there is formed second resist mask 175 for covering the sidewalls of opening 169 and portions other than opening 169.
Next, as shown in FIG. 36A, interlayer insulating film 153 is etched using second resist mask 175 as a mask to form opening 177 including pad electrode 155 as the bottom face thereof. This opening 177, along with opening 169, composes through-hole H. The etching of this interlayer insulating film 153 is carried out by dry etching using a mixed gas composed of, for example, CF4, CHF3, C2F6, O2, He and the like. After this, second resist mask 175 is removed (FIG. 36B).
Next, as shown in FIG. 36C, underlying metal film 173 (for example, Au, Ti, or Ni) is formed using a sputtering method on the entire rear surface of silicon substrate 1 in which through-hole H has been formed.
Next, as shown in FIG. 37A, a region in which a plug electrode including through-hole H is to be formed is exposed and third resist mask 179 covering portions other than the region is formed on underlying metal film 173. After this, as shown in FIG. 37B, a metal material, such as copper, is deposited on underlying metal film 173 by electrolytic plating and nonelectrolytic plating, so as to fill through-hole H exposed from below this resist mask 179, thereby forming electrode 181. After forming this electrode 181, third resist mask 179 is removed as shown in FIG. 37C.
After this, as shown in FIG. 38, underlying metal film 173 exposed from below electrode 181 is etched and removed. Then, surface protection film 161 present on the front surface side of silicon substrate 151 is etched and removed to complete IC chip 150.
In the method for manufacturing a semiconductor device including a through-hole disclosed in Japanese Patent Laid-Open No. 2005-93486, however, a photolithographic technique is used twice when processing the opening from the rear surface. In addition, the type of etching gas is changed after etching silicon substrate 151, and then interlayer insulating film 153 is etched. This Japanese Patent Laid-Open No. 2005-93486 discloses that an etching gas, such as an SF6 or SF6/O2-based etching gas, is used for the etching of silicon substrate 151 and a mixed gas composed of CF4, CHF3, C2F6, O2, He and the like is used for the subsequent etching of interlayer insulating film 153. This means that these two types of etching need to be carried out using separate apparatus (separate chambers), thus involving transferring a semiconductor wafer at each time of etching. Consequently, the above-described method causes not only the prolongation of the manufacturing period of the semiconductor device but also an increase in the cost of manufacture.
In addition, as described above, separate photolithographic techniques are required for the etching of silicon substrate 151 and interlayer insulating film 153. This results in the problem of variation caused when creating openings by etching silicon substrate 151 and interlayer insulating film 153. In particular, the thickness of interlayer insulating film 153 itself varies due to an in-plane variation, a plane-to-plane variation, or a lot-to-lot variation in a semiconductor wafer caused by a film-forming apparatus at the time of film-forming and due to a variation in the semiconductor wafer caused by a CMP apparatus used to planarize the wafer. Consequently, a failure of creating a contact hole for contact with a metal layer (pad electrode) due to under-etching or damage to the metal layer (pad electrode) due to over-etching is caused by a variation in the thickness of interlayer insulating film 153 in a through-hole electrode where an opening is to be created by etching.
Furthermore, there arises the need to add a step of measuring this film thickness, as well as a step of additional growth if the film thickness is thin or a step of etching or the like if the film thickness is too thick, in order to suppress this variation in the thickness of interlayer insulating film 153. Also in this regard, the above-described method causes the prolongation of the manufacturing period of the semiconductor device and an increase in the cost of manufacture.
The present inventors have recognized that if a polysilicon contact pad made of polysilicon is provided as a conductive pad in at least an insulating layer in contact with a semiconductor silicon layer, it is possible to form a via hole both in the semiconductor silicon layer and in the conductive polysilicon within the insulating layer in a single step, since both this polysilicon contact pad and the semiconductor silicon layer are made of silicon. The inventor has thus achieved the present invention.